The present invention relates to a semiconductor integrated circuit and, particularly, to a semiconductor integrated circuit capable of generating a reset signal reliably when power failure has occurred and also when the power voltage is built up slowly.
The magnetic bubble memory is attractive due to its various advantages such as high storage density, non-volatility and low power dissipation, and the development for putting it into practice is now under way. The magnetic bubble memory must be nonvolatile even in the occurrence of power failure or disconnection of the power source. The magnetic bubble memory is generally accompanied by an electronic circuit such as a bubble memory controller for controlling and driving memory cells, and if the circuit operates inordinately upon the occurrence of power failure, non-volatility of the bubble memory will be lost. Namely, upon the occurrence of power failure, the control circuit detects the power voltage falling below a certain level and performs a specified process. On the other hand, however, if the power voltage recovers before falling down to 0 volt, the power-ON reset circuit does not operate and the control circuit cannot start normally.
This is a problem which can occur not only in the magnetic bubble memory, but also in any electronic circuit which performs sequential control and is required to be prevented from abnormally operating at the occurrence of power failure.
For example, it has been a common practice in semiconductor integrated circuits such as microcomputers to constantly provide a charging current for a capacitor 3 from a power source 1 through a resistor 2 of high resistance, and apply the voltage appearing across the capacitor 3 to an integrated circuit 10 through an input pin 5 as shown in FIG. 1A. A diode 4 is used to discharge the capacitor 3 quickly. A logical gate or Schmitt trigger circuit 6 is provided within the integrated circuit 10 so that it generates a reset signal "RESET" when the voltage at the input pin falls below a certain level, thereby preventing the integrated circuit 10 from malfunctioning.
The Schmitt trigger circuit 6 is a bistable circuit operating along the S-shaped curve (hysteresis curve) as shown in FIG. 1B, and the circuit provides an output voltage V.sub.0 at a low level V.sub.L for an input voltage v below V.sub.1 and the output voltage V.sub.0 makes a quick transition to a high level V.sub.H when the input voltage v goes above the level V.sub.1. Furthermore, when the input voltage v is initially higher than V.sub.1, the output voltage V.sub.0 maintains the high level V.sub.H for an input voltage above V.sub.2 and it makes a quick transition to the low level V.sub.L when the input voltage falls below the level V.sub.2.
Accordingly, by the operation of making the output voltage V.sub.0 rise to the high level V.sub.H when the supply voltage v reaches V.sub.1, the reset signal can be released, and by the operation of making the output voltage V.sub.0 fall to the low level V.sub.L when the supply voltage v falls abnormally below V.sub.2, the reset signal can be activated.
However, the reset signal generating circuit shown in FIG. 1A uses the input voltage signal derived from the voltage of the power source 1 with its build-up being delayed by the CR delay circuit consisting of the resistor 2 and capacitor 3, and therefore, if the power source voltage during the power-ON operation is built up at a slower rate relative to the CR time constant, or if the power voltage falls due to an abnormality at a slower rate relative to the CR time constant, the input voltage signal at the input pin 5 will be substantially the same as the power voltage. Accordingly, in most cases, the logic circuit within the integrated circuit 10 has already lost its normal operation and can not generate the reset signal normally by the time the signal level at the input pin 5 reaches the threshold level of the receiving logic circuit.
There is proposed a logic circuit which, when the power voltage falls abnormally or the power source has been disconnected, memorizes the logical states immediately before the time when the normal voltage is lost and restarts the logical operation on the basis of the memorized logical states when the power voltage is restored, as disclosed in Japanese Patent Application Laid-open No. 119534/75. This circuit has a voltage detector 23, as shown in FIG. 2A, which detects the abnormal fall in the voltage of a power source 1 to deenergize a normally operating relay 24 so that a capacitor 3 is disconnected from ground. This allows the capacitor 3 to gradually discharge its stored electric charge through a resistor 21 of high resistance, whereby the electric charge immediately before the abnormal voltage fall can be held for a long time.
As shown by V in FIG. 2B, when the power voltage returns to a normal voltage above a certain level V.sub.R, the detector 23 energizes the relay 24 and, at the same time, activates a pulse generator 7 to generate a single pulse 25 so that an AND gate 9 is disabled through an inverter 8. Consequently, the input signal "IN" is inhibited from the entry to the logic circuit, and the charged voltage corresponding to the logical level of the IN signal immediately before the abnormal fall in the power voltage is applied through the resistor 21 to the buffer amplifier 22 and sent out as an output signal "OUT". The arrangement of FIG. 2A can operate the relay 24 and pulse generator 7 at an exact time point even if the power voltage falls or rises slowly. However, it is difficult to pack the relay 24 and the associated contacts 24' within the package of the integrated circuit.
The following reference is cited to show the state of the art:
Japanese Patent Application Laid-open No. 119534/75.